1. Field of the Invention
The present invention relates to a method and apparatus for patterning, shaping and/or altering the backside surface of a semiconductor die. The present invention improves adhesion between a back side surface of a semiconductor die and either a die attach adhesive or encapsulation compound, reduces adhesive contamination from semiconductor wafer tape used in wafer processing, and reduces shear stress along the interface between the semiconductor die back side surface and either the die attach adhesive and/or encapsulation compound.
2. State of the Art
In a typical integrated circuit manufacturing process, a plurality of sets of integrated circuit patterns are simultaneously formed in discrete locations on a surface of a semiconductor wafer by a series of layer deposition and etching processes, as known in the art. Each set of the integrated circuit patterns is generally formed in a series of rectangular formats on a surface of the semiconductor wafer. Each set of integrated circuit patterns is separated from another set of integrated circuit patterns on the surface of the wafer by an area located therebetween where no integrated circuits or circuits are located on the surface of the wafer. Such an area separating each set of integrated circuits on the surface of the wafer being generally referred to as a "street area" on the surface of the wafer. After the sets of integrated circuit patterns are fully formed, the semiconductor wafer is diced by a wafer sawing machine, as known in the art, along the street areas of the semiconductor wafer separating the semiconductor wafer into a plurality of individual semiconductor dice having a plurality of integrated circuits. These individual semiconductor dice can then either be packaged within protective packages or incorporated into appropriate electronic circuits as unpackaged, or "bare", semiconductor die.
The term "semiconductor wafer" is used herein to denote any solid semiconductor surface, such as is provided by a silicon, gallium arsenide or indium phosphide wafer sliced transversely from a crystal ingot, or a layer of such semiconductor material formed on glass, ceramic, sapphire, or other supporting carrier, as known in the art.
Once a semiconductor wafer has been sliced or otherwise formed, such as being sawed from a crystal ingot, a surface of the semiconductor wafer may undergo a rough polish followed by chemical-mechanical polishing process ("CMP process") to free the surface of irregularities and/or saw damage for the subsequent formation of the integrated circuit patterns thereon. Rough polishing of a surface of the semiconductor wafer generally includes an abrasive, slurry lapping process, as known in the art. The CMP process used after a rough polish of a surface of the wafer includes a combination of chemical etching and mechanical buffing wherein a mild etchant solution is flooded over the semiconductor wafer forming a thin etched chemical layer of a surface of the semiconductor wafer that is removed by the mechanical buffing action. The combination of the rough polish followed by CMP process results in a mirror-like finish on a surface of the semiconductor wafer. The term "mirror-like finish" is generally defined as a semiconductor wafer surface flatness value typically ranging from 3 to 4 .mu.m as measured by the maximum peak-to-valley deviation of a semiconductor wafer surface from a reference plane extending thereover.
Generally, semiconductor wafers are initially sliced or otherwise fabricated having a thickness greater than is desired for a finished integrated circuit semiconductor die formed therefrom. A thick semiconductor wafer is more robust, which minimizes warpage and breakage that can result from various heating processes, as well as other processes, during the formation of the integrated circuit patterns for the semiconductor dice on a polished surface of the semiconductor wafer.
However, the thick semiconductor wafer is typically thicker than is desired for packaging of the individual semiconductor die, or too thick for use with processing equipment and fixtures in subsequent semiconductor die processing and/or encapsulation steps. Therefore, it is usually necessary, after the integrated circuit patterns are defined on the polished surface of the semiconductor wafer, to grind or otherwise remove a portion of the back side surface of the semiconductor wafer (i.e., the side opposite to the polished surface having a mirror-like finish of the semiconductor wafer) in order to reduce the semiconductor wafer thickness prior to the semiconductor wafer being diced into individual semiconductor die. Suitable grinding, sawing machines, and other processes and equipment for removing excess wafer depth on the semiconductor wafer back side surface are well known in the art.
To prevent movement of portions of the semiconductor wafer during the sawing process used to form individual semiconductor dice, a piece of semiconductor wafer tape is temporarily secured to the back side surface of the semiconductor wafer. Semiconductor wafer tape typically comprises an adhesive, a base film, and a release liner. The semiconductor wafer tape typically has a thickness in the range of about 5 to 15 .mu.m. The semiconductor wafer tape adhesive is typically composed of five components: a base polymer, a cross-linking agent, an oligomer, a photo-initiator, and an additive agent. The base polymer comprises the main structural element of the adhesive of the semiconductor wafer tape. The oligomer serves to adjust the adhesive strength and hardness of the adhesive, so that an individual integrated circuit semiconductor die can be easily removed from the semiconductor wafer tape. The cross-linking agent is designed to enhance the cohesion of the adhesive of the semiconductor wafer tape. The photo-initiator enhances the degree of bonding by creating radicals during exposure to UV radiation after the semiconductor wafer tape is applied to the back side surface of the semiconductor wafer. Lastly, the additive agent acts to modify the strength of the adhesive of the semiconductor wafer tape independently of the oligomer. After application to the back side of the semiconductor wafer, the semiconductor wafer tape is exposed to ultraviolet radiation to trigger a chemical reaction to render the tape adhesive. (See, M. Amagai, et al., "Cracking Failures in Lead-On-Chip Packages Induced by Chip Back side Contamination", IEEE Transactions On Components, Packaging And Manufacturing Technology, Part B, Vol. 18, No. 1, pp. 119-126 (1995) (hereinafter "the Amagai article")).
After sawing the semiconductor wafer to form individual semiconductor die, the individual, or "singulated", semiconductor dice are removed from the semiconductor wafer tape. Although the taping of the semiconductor wafer is necessary, it results in adhesive and/or residues (primarily base polymer, oligomer, and additives) remaining on the back side of each of the individual semiconductor dice. These contaminants (adhesive and/or residues) affect the quality of the bond between the individual semiconductor die and an encapsulation compound (such as an epoxy molding resin) which may surround the semiconductor die used in the packaging of the die, or the quality of the bond between the semiconductor die and a substrate to which the semiconductor die may be mounted by a die attach adhesive (such as an epoxy adhesive). The failure to form a high quality bond may then result in interfacial delamination between the back side surface of the semiconductor die and either the encapsulation compound or the die attach adhesive. Thereafter, moisture absorbed into either the encapsulation compound or the die attach adhesive may collect in the delaminated areas where subsequent higher temperatures can convert the moisture to steam. The formation of steam may crack either the encapsulation compound or die attach adhesive or further delaminate the semiconductor die from either the encapsulation compound or die attach adhesive.
Furthermore, interfacial delamination caused by the lack of a high quality bond may be exacerbated by thermal mismatch due to differing coefficients of thermal expansion ("CTE") between the semiconductor die and either the encapsulation compound or the die attach adhesive. As the semiconductor die is thermally cycled by heating and cooling during fabrication processes, the interfacial delamination causes a high stress concentration in any encapsulation compound (particularly at a corners thereof) or the die attach adhesive which, in turn, can cause cracks. Once cracks are formed in either the encapsulation compound or die attach adhesive, the semiconductor package is susceptible to contamination which can render the semiconductor die inoperative.
Moreover, as higher performance, lower cost, increased miniaturization of components and greater packaging density of semiconductor die occur, related semiconductor die problems increase, such as package cracking, contamination, poor semiconductor die-to-encapsulation compound adhesion, and poor semiconductor die-to-substrate adhesion.
In an effort to combat these problems, various techniques have been suggested. Two common temporary solutions include baking the moisture out of the mold compound to ensure a low moisture content within the package, and placing the packaged semiconductor device in a "dry package" for shipping purposes. However, neither solution prevents moisture from entering the packaged semiconductor device at a later time, such as at the customer's site after the device is removed from the shipping container materials. Furthermore, these solutions do not address the CTE problems. Moreover, if the semiconductor die has delaminated even slightly in the from the encapsulation compound forming the package, the package may be subject to moisture penetration after installation causing the package to crack or delaminate when exposed to sufficient heat.
U.S. Pat. No. 5,583,372 (hereinafter "the '372 Patent"), issued to King et al., assigned to the assignee of the present invention, discloses a semiconductor die including a metal layer deposited thereon for enhancing adhesion between the semiconductor die and a mold compound (i.e., an encapsulant compound). The metal layer is substantially oxide free and provides a uniform wetting surface for better adhesion. However, the semiconductor die of the '372 Patent does not prevent or reduce contamination due to the semiconductor wafer tape. Furthermore, the '372 Patent requires additional materials and fabrication processing; specifically, depositing approximately 50 micro inches of copper on the back side surface of the semiconductor die and approximately 2 to 3 micro inches of palladium over the copper layer to form the metal layer.
U.S. Pat. No. 5,313,102 (hereinafter "the '102 Patent"), issued to Lim et al., discloses a "leads-on-chip" (hereinafter "LOC") semiconductor package device wherein a polyimide coating is placed on a back side surface of the integrated circuit prior to encapsulation to improve adhesion between the back side surface of the integrated circuit and the encapsulation compound. However, the semiconductor package device of the '102 Patent does not prevent or reduce contamination to the back side surface of the semiconductor wafer or to the polyimide coating due to the semiconductor wafer tape. Moreover, the polyimide coating fails to correct shearing problems due to differing CTEs between the semiconductor wafer and die attach adhesives or encapsulants.
U.S. Pat. No. 5,756,380 (hereinafter "the '380 Patent"), issued to Berg et al., discloses a method for making moisture resistant semiconductor devices, such as a plastic ball grid array packages, having a semiconductor die attached to an organic substrate by a silicone based die attach material after undergoing a cleaning operation to remove contaminants from the back side surface of the semiconductor die and prior to encapsulation. However, the '380 Patent requires the added processing step of cleaning using an ultraviolet light and ozone cleaning operation and does not compensate for, reduce, and/or eliminate potential shearing problems or thermal mismatching problems due to materials having dissimilar CTEs.
Finally, the Amagai article, previously referenced, discloses that adhesives with a high elastic modulus (i.e. materials which could be peeled without leaving residues) eliminate semiconductor wafer tape contamination and also improve the wettability of the chip back side surface. However, usage of the new semiconductor wafer tape disclosed in the Amagai article does not compensate for nor reduce or eliminate the potential thermal mismatching problems and resultant shear forces due to materials having dissimilar CTEs.
Thus, it can be appreciated that it would be advantageous to develop a semiconductor die and a technique to fabricate the same which overcomes the problems associated with contamination by the semiconductor wafer tape, thermal mismatch, and poor back side adhesion between the back side surface of the semiconductor die and either the encapsulation compounds or die attach adhesives.